1. Field of the Invention
The present invention generally relates to digital data processing devices and, more particularly, to a shifter circuit for multiplexing bytes of data into various orders on a finite size bus.
2. Prior Art
In byte-slice digital data processing devices, the bytes of data (eight bits to a byte) are often scrambled from one order of bytes to another. The term "order" as used herein refers to the digital position of a byte of data such as high-order versus low-order position. When it becomes necessary to transfer a multiple-byte word along a data path to other devices or parts of a device, it may also be necessary to rearrange the order of the bytes into a preferred positional arrangement.
More particularly, in computer systems having large memories, it is desirable to group bytes of digital information into units or words large enough to efficiently perform error detection and correction. In addition, to avoid placing undue constraints on the software, it is desirable to randomly select bytes, half words or words from the memory. That is, the memory addressing is arranged so that it is possible to select any contiguous group of one, two or four bytes. To aid in doing this, the memory is divided into odd and even 32-bit words. However, this odd-even organization scheme must be disguised from the software. To this end, it is necessary to rearrange the order of the bytes into the order in which the software expects them to be written in the memory; that is, the order as originally written by the software. Hence, a circuit is required for rearranging the byte order.
One such prior art circuit used in byte rearranging is shown in FIG. 1. Two 32-bit buses 11 and 12 are each organized into four sub-buses 13 through 20 and are disposed for transmitting the four bytes supplied on each of the buses. The sub-buses are coupled to input terminals of four 64-to-8 multiplexor circuits 22, 23, 24 and 25. The eight-bit outputs of these multiplexor circuits are coupled in parallel so as to form a 32-bit output bus 26. Each of the four multiplexors 22, 23, 24 and 25 operate in response to three control signals coupled to each of the multiplexors on lines 28, 29, 30 and 31, respectively.
More specifically, the sub-buses 13 through 20 are coupled sequentially to the input terminals of the multiplexor 22. That is, the first byte on the first sub-bus 13 is coupled to the first byte input terminals A of the multiplexor 22, the second byte on the second sub-bus 14 is coupled to the second byte input terminals B of the same multiplexor 22, and so forth for the remaining bytes. However, the sub-bus couplings to the multiplexor 23 are shifted by one byte from that of the multiplexor 22. That is, the sub-bus 13 is coupled to the input terminal D of the multiplexor 23; the sub-bus 14 is coupled to the input terminal A of the multiplexor 23; etc. In a similar manner, the sub-bus couplings to the multiplexor 24 are again shifted by one byte, and the sub-bus couplings to the multiplexor 25 are shifted yet again by one byte to complete all possible byte arrangements for a bus.
In response to the control signals on the lines 28 through 30, the multiplexors 22 through 25 select one set of the input terminals to be coupled to the output terminals of the multiplexor. A shifter circuit as illustrated in FIG. 1 and described above requires a large number of input lines having many cross-overs. Thus, such a circuit becomes a very large and slow circuit when reduced to an integrated circuit.